Modern day integrated chips contain millions of semiconductor devices. The semiconductor devices are electrically connected by way of back-end-of-the-line metallization layers that are formed above the devices on an integrated chip. A typical integrated chip comprises a plurality of back-end-of-the-line metallization layers including different sized metal conductors vertically coupled together with metal contacts (e.g., vias).
Back-end-of-the-line metallization layers are often formed using a dual damascene process. In a dual damascene process, a dielectric material is deposited (e.g., low-k dielectric, ultra low-k dielectric) onto the surface of a semiconductor substrate. The dielectric material is then selectively etched to form openings in the dielectric material for a via layer and for an adjoining metal layer. In a typical via-first dual damascene process, a via hole is first etched through two dielectric layers separated by an etch stop layer. A metal line trench is then formed on top of the via hole. After the via and trench are formed, a diffusion barrier layer and a seed layer are deposited within the openings. An electro-chemical plating process is then used to fill the via and metal trenches with metal (e.g., copper) at the same time. Finally, the surface of the substrate is planarized using a chemical mechanical polishing process to remove any excess metal.
As semiconductor device sizes continue to shrink, the dual damascene process will see a number of potential problems that may affect the quality of the metallization layers. For example, in a 20-namometer (nm) fabrication process, the openings may become too narrow and thus may not be properly filled by conventional dual damascene processes. The top portion of the opening may be blocked, which may create a void underneath that may degrade the performance of the semiconductor device. This problem is particularly acute in high aspect ratio features of small width.
Another problem often seen with dual damascene processes is that etching may damage the dielectric material during a photoresist stripping (e.g., damage to the dielectric trench sidewalls). Such etching defects may result in voids or pit defects that negatively affect the reliability of the metallization layers.